// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright 2019 NXP */ /dts-v1/; #include #include "imx8mp.dtsi" / { model = "NXP i.MX8MPlus EVK board"; compatible = "fsl,imx8mp-evk", "fsl,imx8mp"; chosen { stdout-path = &uart2; }; gpio-leds { compatible = "gpio-leds"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_led>; status { label = "yellow:status"; gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; memory@40000000 { device_type = "memory"; reg = <0x0 0x40000000 0 0xc0000000>, <0x1 0x00000000 0 0xc0000000>; }; wifi_pwrseq: wifi-pwrseq { compatible = "mmc-pwrseq-simple"; regulator-name = "wifi-pwrseq"; pinctrl-names = "default"; reset-gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; post-power-on-delay-ms = <150>; }; reg_bt: regulator-bt { compatible = "regulator-fixed"; regulator-name = "bt"; gpio = <&gpio5 11 GPIO_ACTIVE_HIGH>; startup-delay-us = <100>; enable-active-high; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; reg_can1_stby: regulator-can1-stby { compatible = "regulator-fixed"; regulator-name = "can1-stby"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan1_reg>; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>; enable-active-high; }; reg_can2_stby: regulator-can2-stby { compatible = "regulator-fixed"; regulator-name = "can2-stby"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan2_reg>; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; enable-active-high; }; reg_usdhc2_vmmc: regulator-usdhc2 { compatible = "regulator-fixed"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; regulator-name = "VSD_3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; enable-active-high; }; reg_audio_pwr: regulator-audio-pwr { compatible = "regulator-fixed"; regulator-name = "audio-pwr"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; enable-active-high; regulator-always-on; }; bt_sco_codec: bt_sco_codec { #sound-dai-cells = <1>; compatible = "linux,bt-sco"; }; sound-bt-sco { compatible = "simple-audio-card"; simple-audio-card,name = "bt-sco-audio"; simple-audio-card,format = "dsp_a"; simple-audio-card,bitclock-inversion; simple-audio-card,frame-master = <&btcpu>; simple-audio-card,bitclock-master = <&btcpu>; btcpu: simple-audio-card,cpu { sound-dai = <&sai2>; dai-tdm-slot-num = <2>; dai-tdm-slot-width = <16>; }; simple-audio-card,codec { sound-dai = <&bt_sco_codec 1>; }; }; sound-hdmi { compatible = "fsl,imx-audio-hdmi"; model = "audio-hdmi"; audio-cpu = <&aud2htx>; hdmi-out; constraint-rate = <44100>, <88200>, <176400>, <32000>, <48000>, <96000>, <192000>; status = "okay"; }; sound-wm8960 { compatible = "fsl,imx-audio-wm8960"; model = "wm8960-audio"; audio-cpu = <&sai3>; audio-codec = <&codec>; audio-asrc = <&easrc>; hp-det-gpio = <&gpio4 28 0>; audio-routing = "Headphone Jack", "HP_L", "Headphone Jack", "HP_R", "Ext Spk", "SPK_LP", "Ext Spk", "SPK_LN", "Ext Spk", "SPK_RP", "Ext Spk", "SPK_RN", "LINPUT1", "Mic Jack", "LINPUT3", "Mic Jack", "Mic Jack", "MICB"; }; sound-micfil { compatible = "fsl,imx-audio-card"; model = "imx-audio-micfil"; pri-dai-link { link-name = "micfil hifi"; format = "i2s"; cpu { sound-dai = <&micfil>; }; }; }; sound-xcvr { compatible = "fsl,imx-audio-card"; model = "imx-audio-xcvr"; pri-dai-link { link-name = "XCVR PCM"; cpu { sound-dai = <&xcvr>; }; }; }; lvds_backlight: lvds_backlight { compatible = "pwm-backlight"; pwms = <&pwm2 0 100000>; status = "okay"; brightness-levels = < 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100>; default-brightness-level = <80>; }; cbtl04gp { compatible = "nxp,cbtl04gp"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_typec_mux>; switch-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>; orientation-switch; port { usb3_data_ss: endpoint { remote-endpoint = <&typec_con_ss>; }; }; }; }; &flexspi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexspi0>; status = "okay"; flash0: mt25qu256aba@0 { reg = <0>; #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; spi-max-frequency = <80000000>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; }; }; &flexcan1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan1>; xceiver-supply = <®_can1_stby>; status = "okay"; }; &flexcan2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan2>; xceiver-supply = <®_can2_stby>; pinctrl-assert-gpios = <&pca6416 3 GPIO_ACTIVE_HIGH>; status = "disabled";/* can2 pin conflict with pdm */ }; &A53_0 { cpu-supply = <&buck2>; }; &A53_1 { cpu-supply = <&buck2>; }; &A53_2 { cpu-supply = <&buck2>; }; &A53_3 { cpu-supply = <&buck2>; }; &dsp { status = "okay"; }; &pwm1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; status = "okay"; }; &pwm2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm2>; status = "okay"; }; &pwm4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm4>; status = "okay"; }; &aud2htx { status = "okay"; }; &ecspi2 { #address-cells = <1>; #size-cells = <0>; fsl,spi-num-chipselects = <1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>; cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; //status = "okay"; status = "disabled"; /* added */ spidev1: spi@0 { reg = <0>; compatible = "rohm,dh2228fv"; spi-max-frequency = <500000>; }; }; &eqos { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_eqos>; phy-mode = "rgmii-id"; phy-handle = <ðphy0>; snps,force_thresh_dma_mode; snps,mtl-tx-config = <&mtl_tx_setup>; snps,mtl-rx-config = <&mtl_rx_setup>; status = "okay"; mdio { compatible = "snps,dwmac-mdio"; #address-cells = <1>; #size-cells = <0>; ethphy0: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; eee-broken-1000t; realtek,clkout-disable; }; }; mtl_tx_setup: tx-queues-config { snps,tx-queues-to-use = <5>; snps,tx-sched-sp; queue0 { snps,dcb-algorithm; snps,priority = <0x1>; }; queue1 { snps,dcb-algorithm; snps,priority = <0x2>; }; queue2 { snps,dcb-algorithm; snps,priority = <0x4>; }; queue3 { snps,dcb-algorithm; snps,priority = <0x8>; }; queue4 { snps,dcb-algorithm; snps,priority = <0xf0>; }; }; mtl_rx_setup: rx-queues-config { snps,rx-queues-to-use = <5>; snps,rx-sched-sp; queue0 { snps,dcb-algorithm; snps,priority = <0x1>; snps,map-to-dma-channel = <0>; }; queue1 { snps,dcb-algorithm; snps,priority = <0x2>; snps,map-to-dma-channel = <1>; }; queue2 { snps,dcb-algorithm; snps,priority = <0x4>; snps,map-to-dma-channel = <2>; }; queue3 { snps,dcb-algorithm; snps,priority = <0x8>; snps,map-to-dma-channel = <3>; }; queue4 { snps,dcb-algorithm; snps,priority = <0xf0>; snps,map-to-dma-channel = <4>; }; }; }; &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec>; phy-mode = "rgmii-id"; phy-handle = <ðphy1>; fsl,magic-packet; status = "okay"; mdio { #address-cells = <1>; #size-cells = <0>; ethphy1: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; eee-broken-1000t; reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; reset-assert-us = <10000>; reset-deassert-us = <80000>; realtek,clkout-disable; }; }; }; &i2c1 { clock-frequency = <400000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; pmic@25 { compatible = "nxp,pca9450c"; reg = <0x25>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pmic>; interrupt-parent = <&gpio1>; interrupts = <3 IRQ_TYPE_LEVEL_LOW>; regulators { buck1: BUCK1 { regulator-name = "BUCK1"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <2187500>; regulator-boot-on; regulator-always-on; regulator-ramp-delay = <3125>; }; buck2: BUCK2 { regulator-name = "BUCK2"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <2187500>; regulator-boot-on; regulator-always-on; regulator-ramp-delay = <3125>; nxp,dvs-run-voltage = <950000>; nxp,dvs-standby-voltage = <850000>; }; buck4: BUCK4{ regulator-name = "BUCK4"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <3400000>; regulator-boot-on; regulator-always-on; }; buck5: BUCK5{ regulator-name = "BUCK5"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <3400000>; regulator-boot-on; regulator-always-on; }; buck6: BUCK6 { regulator-name = "BUCK6"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <3400000>; regulator-boot-on; regulator-always-on; }; ldo1: LDO1 { regulator-name = "LDO1"; regulator-min-microvolt = <1600000>; regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; ldo2: LDO2 { regulator-name = "LDO2"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <1150000>; regulator-boot-on; regulator-always-on; }; ldo3: LDO3 { regulator-name = "LDO3"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; ldo4: LDO4 { regulator-name = "LDO4"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; ldo5: LDO5 { regulator-name = "LDO5"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; }; }; }; &i2c2 { clock-frequency = <100000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; adv_bridge: adv7535@3d { compatible = "adi,adv7535"; reg = <0x3d>; adi,addr-cec = <0x3b>; adi,dsi-lanes = <4>; status = "okay"; port { adv7535_from_dsim: endpoint { remote-endpoint = <&dsim_to_adv7535>; }; }; }; lvds_bridge: lvds-to-hdmi-bridge@4c { compatible = "ite,it6263"; reg = <0x4c>; reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; port { it6263_in: endpoint { remote-endpoint = <&lvds_out>; }; }; }; ov5640_0: ov5640_mipi@3c { compatible = "ovti,ov5640"; reg = <0x3c>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_csi0_pwn>, <&pinctrl_csi0_rst>, <&pinctrl_csi_mclk>; clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; clock-names = "xclk"; assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; assigned-clock-parents = <&clk IMX8MP_CLK_24M>; assigned-clock-rates = <24000000>; csi_id = <0>; powerdown-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; mclk = <24000000>; mclk_source = <0>; mipi_csi; status = "okay"; port { ov5640_mipi_0_ep: endpoint { remote-endpoint = <&mipi_csi0_ep>; data-lanes = <1 2>; clock-lanes = <0>; }; }; }; ptn5110: tcpc@50 { compatible = "nxp,ptn5110"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_typec>; reg = <0x50>; interrupt-parent = <&gpio4>; interrupts = <19 8>; port { typec_dr_sw: endpoint { remote-endpoint = <&usb3_drd_sw>; }; }; usb_con: connector { compatible = "usb-c-connector"; label = "USB-C"; power-role = "dual"; data-role = "dual"; try-power-role = "sink"; source-pdos = ; sink-pdos = ; op-sink-microwatt = <15000000>; self-powered; ports { #address-cells = <1>; #size-cells = <0>; port@1 { reg = <1>; typec_con_ss: endpoint { remote-endpoint = <&usb3_data_ss>; }; }; }; }; }; }; &i2c3 { clock-frequency = <400000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; pca6416: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; }; codec: wm8960@1a { compatible = "wlf,wm8960"; reg = <0x1a>; clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK1>; clock-names = "mclk"; wlf,shared-lrclk; wlf,hp-cfg = <3 2 3>; wlf,gpio-cfg = <1 3>; SPKVDD1-supply = <®_audio_pwr>; }; ov5640_1: ov5640_mipi@3c { compatible = "ovti,ov5640"; reg = <0x3c>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_csi0_pwn>, <&pinctrl_csi0_rst>, <&pinctrl_csi_mclk>; clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; clock-names = "xclk"; assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; assigned-clock-parents = <&clk IMX8MP_CLK_24M>; assigned-clock-rates = <24000000>; csi_id = <0>; powerdown-gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>; reset-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; mclk = <24000000>; mclk_source = <0>; mipi_csi; status = "disabled"; port { ov5640_mipi_1_ep: endpoint { remote-endpoint = <&mipi_csi1_ep>; data-lanes = <1 2>; clock-lanes = <0>; }; }; }; }; &irqsteer_hdmi { status = "okay"; }; &hdmi_blk_ctrl { status = "okay"; }; &hdmi_pavi { status = "okay"; }; &hdmi { status = "okay"; }; &hdmiphy { status = "okay"; }; &lcdif1 { status = "okay"; }; &lcdif2 { status = "okay"; }; &lcdif3 { status = "okay"; thres-low = <1 2>; /* (FIFO * 1 / 2) */ thres-high = <3 4>; /* (FIFO * 3 / 4) */ }; &ldb { status = "okay"; lvds-channel@0 { fsl,data-mapping = "jeida"; fsl,data-width = <24>; status = "okay"; port@1 { reg = <1>; lvds_out: endpoint { remote-endpoint = <&it6263_in>; }; }; }; }; &ldb_phy { status = "okay"; }; &mipi_dsi { status = "okay"; port@1 { dsim_to_adv7535: endpoint { remote-endpoint = <&adv7535_from_dsim>; attach-bridge; }; }; }; &snvs_pwrkey { status = "okay"; }; &easrc { fsl,asrc-rate = <48000>; status = "okay"; }; &micfil { #sound-dai-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pdm>; assigned-clocks = <&clk IMX8MP_CLK_PDM>; assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; assigned-clock-rates = <196608000>; status = "okay"; }; &pcie{ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie>; disable-gpio = <&gpio2 6 GPIO_ACTIVE_LOW>; reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>; ext_osc = <1>; clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, <&clk IMX8MP_CLK_PCIE_AUX>, <&clk IMX8MP_CLK_HSIO_AXI>, <&clk IMX8MP_CLK_PCIE_ROOT>; clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>, <&clk IMX8MP_CLK_PCIE_AUX>; assigned-clock-rates = <500000000>, <10000000>; assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>, <&clk IMX8MP_SYS_PLL2_50M>; l1ss-disabled; status = "okay"; wifi_wake_host { compatible = "nxp,wifi-wake-host"; interrupt-parent = <&gpio5>; interrupts = <21 IRQ_TYPE_LEVEL_LOW>; interrupt-names = "host-wake"; }; }; &pcie_ep{ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie>; ext_osc = <1>; clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, <&clk IMX8MP_CLK_PCIE_AUX>, <&clk IMX8MP_CLK_HSIO_AXI>, <&clk IMX8MP_CLK_PCIE_ROOT>; clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>, <&clk IMX8MP_CLK_PCIE_AUX>; assigned-clock-rates = <500000000>, <10000000>; assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>, <&clk IMX8MP_SYS_PLL2_50M>; status = "disabled"; }; &pcie_phy{ ext_osc = <1>; status = "okay"; }; &sai2 { #sound-dai-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai2>; assigned-clocks = <&clk IMX8MP_CLK_SAI2>; assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; assigned-clock-rates = <12288000>; status = "okay"; }; &sai3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai3>; assigned-clocks = <&clk IMX8MP_CLK_SAI3>; assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; assigned-clock-rates = <12288000>; clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_IPG>, <&clk IMX8MP_CLK_DUMMY>, <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, <&clk IMX8MP_CLK_DUMMY>; clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; fsl,sai-mclk-direction-output; status = "okay"; }; &xcvr { #sound-dai-cells = <0>; status = "okay"; }; &sdma2 { status = "okay"; }; &uart1 { /* BT */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; assigned-clocks = <&clk IMX8MP_CLK_UART1>; assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; fsl,uart-has-rtscts; status = "okay"; }; &uart2 { /* console */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; status = "okay"; }; &usb3_phy0 { vbus-power-supply = <&ptn5110>; fsl,phy-tx-vref-tune = <0xe>; fsl,phy-tx-preemp-amp-tune = <3>; fsl,phy-tx-vboost-level = <5>; fsl,phy-comp-dis-tune = <7>; fsl,pcs-tx-deemph-3p5db = <0x21>; fsl,phy-pcs-tx-swing-full = <0x7f>; status = "okay"; }; &usb3_0 { status = "okay"; }; &usb_dwc3_0 { dr_mode = "otg"; hnp-disable; srp-disable; adp-disable; usb-role-switch; role-switch-default-mode = "none"; snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; status = "okay"; port { usb3_drd_sw: endpoint { remote-endpoint = <&typec_dr_sw>; }; }; }; &usb3_phy1 { fsl,phy-tx-preemp-amp-tune = <3>; fsl,phy-tx-vref-tune = <0xb>; status = "okay"; }; &usb3_1 { status = "okay"; }; &usb_dwc3_1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1_vbus>; dr_mode = "host"; status = "okay"; }; &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; assigned-clocks = <&clk IMX8MP_CLK_UART3>; assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; fsl,uart-has-rtscts; status = "okay"; }; &usdhc2 { assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; assigned-clock-rates = <400000000>; pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; max-frequency = <100000000>; cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; vmmc-supply = <®_usdhc2_vmmc>; mmc-pwrseq = <&wifi_pwrseq>; bus-width = <4>; status = "okay"; }; &usdhc3 { assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; assigned-clock-rates = <400000000>; pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc3>; pinctrl-1 = <&pinctrl_usdhc3_100mhz>; pinctrl-2 = <&pinctrl_usdhc3_200mhz>; bus-width = <8>; non-removable; status = "okay"; }; &wdog1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_wdog>; fsl,ext-reset-output; status = "okay"; }; &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog>; pinctrl_hog: hoggrp { fsl,pins = < MX8MP_IOMUXC_ECSPI2_MOSI__GPIO5_IO11 0x00000146 MX8MP_IOMUXC_ECSPI2_SCLK__GPIO5_IO10 0x00000146 MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c3 MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c3 MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000019 MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000019 >; }; pinctrl_pwm1: pwm1grp { fsl,pins = < MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x116 >; }; pinctrl_pwm2: pwm2grp { fsl,pins = < MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x116 >; }; pinctrl_pwm4: pwm4grp { fsl,pins = < MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT 0x116 >; }; pinctrl_ecspi2: ecspi2grp { fsl,pins = < MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82 MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82 MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82 >; }; pinctrl_ecspi2_cs: ecspi2cs { fsl,pins = < MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40000 >; }; pinctrl_eqos: eqosgrp { fsl,pins = < MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x19 >; }; pinctrl_fec: fecgrp { fsl,pins = < MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x19 >; }; pinctrl_flexcan1: flexcan1grp { fsl,pins = < MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 >; }; pinctrl_flexcan2: flexcan2grp { fsl,pins = < MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 >; }; pinctrl_flexcan1_reg: flexcan1reggrp { fsl,pins = < MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 /* CAN1_STBY */ >; }; pinctrl_flexcan2_reg: flexcan2reggrp { fsl,pins = < MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x154 /* CAN2_STBY */ >; }; pinctrl_flexspi0: flexspi0grp { fsl,pins = < MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 >; }; pinctrl_gpio_led: gpioledgrp { fsl,pins = < MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19 >; }; pinctrl_i2c1: i2c1grp { fsl,pins = < MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 >; }; pinctrl_i2c2: i2c2grp { fsl,pins = < MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 >; }; pinctrl_i2c3: i2c3grp { fsl,pins = < MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 >; }; pinctrl_mipi_dsi_en: mipi_dsi_en { fsl,pins = < MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x16 >; }; pinctrl_pcie: pciegrp { fsl,pins = < MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x61 /* open drain, pull up */ MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x41 MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x41 MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x1c4 >; }; pinctrl_pmic: pmicgrp { fsl,pins = < MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x000001c0 >; }; pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { fsl,pins = < MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 >; }; pinctrl_pdm: pdmgrp { fsl,pins = < MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_PDM_CLK 0xd6 MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_PDM_BIT_STREAM00 0xd6 MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_PDM_BIT_STREAM01 0xd6 MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_PDM_BIT_STREAM02 0xd6 MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_PDM_BIT_STREAM03 0xd6 >; }; pinctrl_sai2: sai2grp { fsl,pins = < MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0xd6 MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0xd6 MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6 MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00 0xd6 >; }; pinctrl_sai3: sai3grp { fsl,pins = < MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6 MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6 MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6 MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6 MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0xd6 MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0xd6 >; }; pinctrl_i2c2_synaptics_dsx_io: synaptics_dsx_iogrp { fsl,pins = < MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x16 >; }; pinctrl_uart1: uart1grp { fsl,pins = < MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140 MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140 >; }; pinctrl_typec: typec1grp { fsl,pins = < MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x1c4 >; }; pinctrl_typec_mux: typec1muxgrp { fsl,pins = < MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x16 >; }; pinctrl_uart2: uart2grp { fsl,pins = < MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49 >; }; pinctrl_usb1_vbus: usb1grp { fsl,pins = < MX8MP_IOMUXC_GPIO1_IO14__USB2_PWR 0x19 >; }; pinctrl_uart3: uart3grp { fsl,pins = < MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140 MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140 MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140 MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140 >; }; pinctrl_usdhc2: usdhc2grp { fsl,pins = < MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 >; }; pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { fsl,pins = < MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 >; }; pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { fsl,pins = < MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 >; }; pinctrl_usdhc2_gpio: usdhc2gpiogrp { fsl,pins = < MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 >; }; pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 >; }; pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { fsl,pins = < MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 >; }; pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { fsl,pins = < MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 >; }; pinctrl_wdog: wdoggrp { fsl,pins = < MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166 >; }; pinctrl_csi0_pwn: csi0_pwn_grp { fsl,pins = < MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x19 >; }; pinctrl_csi0_rst: csi0_rst_grp { fsl,pins = < MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x19 >; }; pinctrl_csi_mclk: csi_mclk_grp { fsl,pins = < MX8MP_IOMUXC_GPIO1_IO15__CCM_CLKO2 0x59 >; }; }; &vpu_g1 { status = "okay"; }; &vpu_g2 { status = "okay"; }; &vpu_vc8000e { status = "okay"; }; &vpu_v4l2 { status = "okay"; }; &gpu_3d { status = "okay"; }; &gpu_2d { status = "okay"; }; &ml_vipsi { status = "okay"; }; &mix_gpu_ml { status = "okay"; }; &mipi_csi_0 { #address-cells = <1>; #size-cells = <0>; status = "okay"; port@0 { reg = <0>; mipi_csi0_ep: endpoint { remote-endpoint = <&ov5640_mipi_0_ep>; data-lanes = <2>; csis-hs-settle = <13>; csis-clk-settle = <2>; csis-wclk; }; }; }; &mipi_csi_1 { #address-cells = <1>; #size-cells = <0>; status = "disabled"; port@1 { reg = <1>; mipi_csi1_ep: endpoint { remote-endpoint = <&ov5640_mipi_1_ep>; data-lanes = <2>; csis-hs-settle = <13>; csis-clk-settle = <2>; csis-wclk; }; }; }; &cameradev { status = "okay"; }; &isi_0 { status = "okay"; cap_device { status = "okay"; }; m2m_device { status = "okay"; }; }; &isi_1 { status = "disabled"; cap_device { status = "okay"; }; };